In signal processing, there often exists a requirement to share a common resource among a plurality of entries (e.g., requestors) for that common resource. A scheduling system performs priority arbitration for granting access to that common resource to a particular entry for a certain period. Such priority arbitration attempts to grant reasonable access to the shared resource for each of the plurality of entries. As the number of entries (also referred to as the entry count) increases, the complexity of the scheduling system increases. As such, performing the priority arbitration by the scheduling system for a larger entry count may require more area in an integrated circuit and causes longer delay in its logic path.
Accordingly, it would be desirable and useful to provide an improved scheduling system.